The instant invention relates to integrated circuit devices which are particularly adapted for high voltage applications. The invention particularly relates to integrated circuit devices which are manufactured by the use of semiconductor-on-insulator (SOI) technology and which devices exhibit improved voltage breakdown properties.
A major problem in high voltage integrated circuit technology is to find a satisfactory solution for the problem of isolation of components and subcircuit sections.
The usual method of electrically isolating components within an integrated circuit and, more particularly, within a power integrated circuit (PIC) or a high voltage integrated circuit (HVIC) is by what is called "junction isolation". In such a method p-type diffusions may be used to isolate various devices formed in a n-type epitaxial layer on top of a silicon substrate. Such a method is described in Rumennik, IEEE Spectrum, Vol. 22, pp. 42-48, July 1985.
Another method of electrical isolation of such components is the so-called "dielectric isolation". In this method, an electrically-insulating material, such as silicon dioxide is used to isolate the individual components such as devices operating at very different electrical potentials. SOI technology when the semiconductor is silicon and the insulator is silicon dioxide (hereinafter referred to as "oxide") is an example of a dielectric isolation method. In this technology the devices are built in a layer of silicon, approximately 0.1-2 .mu.m thick which is separated from the silicon substrate by a dielectric layer such as silicon oxide typically 0.1-5 .mu.m thick.
Several methods are known for producing the SOI starting material. In one of these methods "SIMOX", silicon oxide is formed by ion implantation of oxygen ions into a silicon wafer.
In another method, zone-melt-recrystallized (ZMR) material is prepared by depositing a polycrystalline silicon layer over an oxide-coated silicon wafer and converting the polycrystalline silicon into a monocrystalline silicon film by irradiating the polycrystalline silicon with a power source such as a laser or a graphite-strip heater.
Another method is the bonding and etchback or direct bonding method in which two oxide-coated silicon wafers are joined together to form a strong bond and one of these wafers is thinned to the desired thickness.
Lateral transistor structures for high voltage applications may be seen by way of a lateral n-channel DMOS (LDMOS) transistor, such as that seen in the article by Rumennik, IEEE Spectrum, Volume 22, July, 1985, pages 42-48. In this article, discussing power integrated circuits, the arrangement of a lateral double-diffused MOS transistor is illustrated in FIG. 4C. It is noted that such lateral MOS transistor enables epitaxial layer thicknesses much smaller than those of vertical devices, and that increasing the distance between the source and drain leads to an increase in the breakdown voltage.
The use of nominally high voltage thin film structures has been previously discussed in the art. For example, the Tuan, U.S. Pat. No. 4,752,814, discusses high voltage thin film transistors using amorphous silicon. In such a structure, a gate electrode and source electrode are vertically superimposed while a drain electrode is displaced laterally from both although at a different vertical level with respect to each. An undoped or lightly doped amorphous silicon layer is provided between the source and drain electrodes to conduct current to the drain electrode under control of the gate electrode. A second gate electrode, also vertically below the first gate electrode and extending laterally closer toward the drain electrode, is provided to increase breakdown voltage. However, the patent is completely silent as to the amount of breakdown voltage.
Several methods have been proposed for improving the breakdown voltage of devices formed in the SOI material.
An offset-gate SOI MOS transistor is described in C. I. Drowley et al (Mat. Res. Symp. Proc., Vol. 33, p. 133, 1984). This article indicates that with the structure shown a breakdown voltage of 38V is achieved.
A method of increasing the breakdown voltage that applies specifically to SIMOX devices is shown in S. Nakashima, IEEE Transactions on Electron Devices, Volume ED-33, No. 1,
January, 1986, pages 126-132. By this technique, only a moderately high breakdown voltage is achieved, generally of about 180V.
In each of these prior art structures forming the background to the present invention, various problems and difficulties occur. Especially high breakdown voltages have not been obtained in the prior art.